`timescale 1ns/1ps
module tb_design_test (/*AUTOARG*/ ) ;

   localparam PERIOD = 10;
   localparam DIV = 25;
   localparam BAUD_DIV_HALF = DIV * 8;
   localparam BAUD_DIV = DIV * 16;
   
   reg button0;
   reg button1;
   reg button2;
   reg button3;

   reg clk_100mhz;
   reg rstn;
   wire uart_tx;
   
   initial begin
      button0 = 1'b1;
      button1 = 1'b1;
      button2 = 1'b1;
      button3 = 1'b1;
      clk_100mhz = 1'b0;
      rstn = 1'b0;
      #100;
      rstn = 1'b1;
      #100;
      @(negedge clk_100mhz)
	button0 = 1'b0;
      #100;
      @(negedge clk_100mhz)
	button0 = 1'b1;
      #(PERIOD * BAUD_DIV * 11);

     @(negedge clk_100mhz)
	button1 = 1'b0;
      #100;
      @(negedge clk_100mhz)
	button1 = 1'b1;
      #(PERIOD * BAUD_DIV * 11);

     @(negedge clk_100mhz)
	button2 = 1'b0;
      #100;
      @(negedge clk_100mhz)
	button2 = 1'b1;
      #(PERIOD * BAUD_DIV * 11);

     @(negedge clk_100mhz)
	button3 = 1'b0;
      #100;
      @(negedge clk_100mhz)
	button3 = 1'b1;
      #(PERIOD * BAUD_DIV * 11);

      $stop();
   end // initial begin

   always #5 clk_100mhz <= ~clk_100mhz;


   design_test u_design_test(
			     .button0(button0),
			     .button1(button1),
			     .button2(button2),
			     .button3(button3),
			     .clk_100mhz(clk_100mhz),
			     .uart_tx(uart_tx),
			     .rstn(rstn)
			     );


  

   
endmodule // design_test
